Crystal Selection

XO stands for crystal oscillator. It's the clock source for many digital and mixed-signal systems. It provides a clean and low noise signal that is needed for many applications such as core logic, physical layer transceivers, and mixed-signal ADCS/DACs sampling clock.

The key parameter for select a crystal is looking for its phase noise. Phase noise can be thought of as how jittery a clock source is with respect to its operational nominal frequency. Beware, this is different from clock stability measured in part per million (PPM), which is a tolerance/accuracy measurement. When looking for phase noise, we are examining the crystal's frequency variance/precision factor. It is looking at the strength of noise with respect to the center crystal frequency (i.e nominal frequency) in the frequency domain. We typically would look at offset 1KHz, 10KHz, 100 kHz away from the center frequency. In practice, we look at noise level due to jitter at 100KHz away from the center frequency measured in dBc (where c stands from carrier frequency (i.e nominal crystal frequency). Remember dBC is a relative measurement with respect to crystal nominal frequency. Typically the phase noise is rated under -130 dBc.

The reason that we want a low phase noise crystal is that it is best to have the cleanest (i.e least amount of jitter) source of clock as the clock distribution source. The phase noise of a crystal can be thought of as an FM, frequency modulated signal, that has jitter noise frequency modulated onto the crystal oscillating frequency. When this FM signal gets mixed down to DC through any nonlinear circuit, the noise signal after downmixing turned into an intermodulation product, especially 2nd order intermodulation product, IM2, this IM2 noise in the DC/baseband raises the noise floor. For instance, in an ADC sampling, the sampling process is mixing processing where two analog signals, the clock source, and the analog signal input, are multiplied in the time domain. This mixing for phase noise and input analog signals raises the noise floor of the analog input signals, and therefore lowers the effective dynamic range of the ADC.

A useful tool for PLL design and analysis is https://www.ti.com/tool/PLLATINUMSIM-SW

Resources:

https://www.analog.com/media/en/technical-documentation/application-notes/AN-756.pdf