Crystal Selection for clocking

XO stands for crystal oscillator. It's the clock source for many digital and mixed-signal systems. It provides a clean and low-noise signal that is needed for many applications such as core logic, physical layer transceivers, and mixed-signal ADCS/DAC sampling clocks.

The key parameter for selecting a crystal is looking for its phase noise. Phase noise can be thought of as how jittery a clock source is with respect to its nominal operational frequency. Beware, this is different from clock stability measured in parts per million (PPM), which is a tolerance or accuracy measurement. When looking for phase noise, we are examining the crystal's frequency variance or precision factor. It is looking at the strength of noise with respect to the center crystal frequency (i.e., the nominal frequency) in the frequency domain. We typically would look at offsets of 1 kHz, 10 kHz, or 100 kHz away from the center frequency. 

In practice, we look at noise level due to jitter at 100 kHz away from the center frequency measured in dBc (where c stands for carrier frequency, i.e., nominal crystal frequency). Remember, dBC is a relative measurement with respect to the crystal nominal frequency. Typically, the phase noise is rated under -130 dBc.

The reason that we want a low-phase noise crystal is that it is best to have the cleanest (i.e., with the least amount of jitter) source of clock as the clock distribution source. The phase noise of a crystal can be thought of as an FM, frequency-modulated signal that has jitter noise frequency-modulated onto the crystal's oscillating frequency. When this FM signal gets mixed down to DC through any nonlinear circuit, the noise signal after downmixing turns into an intermodulation product, especially a 2nd-order intermodulation product, IM2. This IM2 noise in the DC/baseband raises the noise floor. For instance, in an ADC sampling process, the sampling process is mixing processing where two analog signals, the clock source and the analog signal input, are multiplied in the time domain. This mixing of phase noise and input analog signals raises the noise floor of the analog input signals and therefore lowers the effective dynamic range of the ADC.

Choose a crystal for your FPGA design

• Determine the required clock frequency: Identify the clock frequency needed for your FPGA design. Consider the operating frequency of your design, including the internal logic and any external interfaces.

• Check FPGA specifications: Consult the datasheet and documentation of the FPGA you are using. Look for the maximum and minimum frequencies supported by the FPGA's clocking resources. Ensure that the crystal you select can provide a frequency within this range.

• Consider stability requirements: Determine the required stability or accuracy of the clock signal. Stability is often specified in parts per million (ppm). Higher stability may be required for applications that demand precise timing, while lower stability may be acceptable for less critical applications.

• Evaluate crystal package size: Consider the available space on your PCB (Printed Circuit Board) and the package size of the crystal. Ensure that the chosen crystal package can be accommodated on your board while considering other components and routing requirements.

• Assess power consumption: Evaluate the power consumption of the crystal oscillator. Lower power consumption can be advantageous, particularly in battery-powered or energy-efficient designs.

• Verify frequency tolerance and aging: Check the frequency tolerance and aging characteristics of the crystal. Frequency tolerance specifies the maximum deviation from the nominal frequency, while aging describes the long-term frequency drift over time. Ensure that the crystal's tolerance and aging characteristics meet your design requirements.

• Consider availability and cost: Verify the availability and cost of the crystal. Ensure that the crystal you select is readily available from reliable suppliers and fits within your budget.

• Consult crystal manufacturer's documentation: Refer to the datasheets and technical information provided by crystal manufacturers. They often provide recommendations and application notes that can assist in selecting the appropriate crystal for FPGA designs.

• Prototype and test: Once you have selected a crystal, prototype your design and perform thorough testing to verify its performance and compatibility with your FPGA. Evaluate factors such as clock stability, jitter, and any impact on the overall system timing.

Practice yourself

A useful tool for PLL design and analysis is https://www.ti.com/tool/PLLATINUMSIM-SW.

Summary

The article discusses the importance of selecting a low-phase noise crystal oscillator (XO) for clocking in digital and mixed-signal systems. Phase noise is highlighted as a key parameter, reflecting the jitter of the clock source with respect to its nominal frequency. The article explains the relationship between phase noise and intermodulation noise, which can affect the performance of components like ADCs. It then provides a step-by-step guide for selecting a crystal for FPGA designs, including considering clock frequency, stability requirements, crystal package size, power consumption, frequency tolerance, aging characteristics, availability, and cost. It emphasizes the need to consult crystal manufacturer documentation, prototype the design, and perform thorough testing to ensure proper performance and compatibility with the FPGA. 

Additional Reading Resources:

https://www.analog.com/media/en/technical-documentation/application-notes/AN-756.pdf