Crystal Selection for clocking

Created:06/15/2021Last Updated:06/15/2021

XO stands for crystal oscillator. It's the clock source for many digital and mixed-signal systems. It provides a clean and low-noise signal that is needed for many applications such as core logic, physical layer transceivers, and mixed-signal ADCS/DAC sampling clocks.

Design Parameters

The key parameter for selecting a crystal is looking for its phase noise. Phase noise can be thought of as how jittery a clock source is with respect to its nominal operational frequency. Beware, this is different from clock stability measured in parts per million (PPM), which is a tolerance or accuracy measurement. When looking for phase noise, we are examining the crystal's frequency variance or precision factor. It is looking at the strength of noise with respect to the center crystal frequency (i.e., the nominal frequency) in the frequency domain. We typically would look at offsets of 1 kHz, 10 kHz, or 100 kHz away from the center frequency. 

In practice, we look at noise level due to jitter at 100 kHz away from the center frequency measured in dBc (where c stands for carrier frequency, i.e., nominal crystal frequency). Remember, dBC is a relative measurement with respect to the crystal nominal frequency. Typically, the phase noise is rated under -130 dBc.

The reason that we want a low-phase noise crystal is that it is best to have the cleanest (i.e., with the least amount of jitter) source of clock as the clock distribution source. The phase noise of a crystal can be thought of as an FM, frequency-modulated signal that has jitter noise frequency-modulated onto the crystal's oscillating frequency. When this FM signal gets mixed down to DC through any nonlinear circuit, the noise signal after downmixing turns into an intermodulation product, especially a 2nd-order intermodulation product, IM2. This IM2 noise in the DC/baseband raises the noise floor. For instance, in an ADC sampling process, the sampling process is mixing processing where two analog signals, the clock source and the analog signal input, are multiplied in the time domain. This mixing of phase noise and input analog signals raises the noise floor of the analog input signals and therefore lowers the effective dynamic range of the ADC.

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The article discusses the importance of selecting a low-phase noise crystal oscillator (XO) for clocking in digital and mixed-signal systems. Phase noise is highlighted as a key parameter, reflecting the jitter of the clock source with respect to its nominal frequency. The article explains the relationship between phase noise and intermodulation noise, which can affect the performance of components like ADCs. It then provides a step-by-step guide for selecting a crystal for FPGA designs, including considering clock frequency, stability requirements, crystal package size, power consumption, frequency tolerance, aging characteristics, availability, and cost. It emphasizes the need to consult crystal manufacturer documentation, prototype the design, and perform thorough testing to ensure proper performance and compatibility with the FPGA. 

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