Signal Integrity
Introduction
Today's electronics is mostly consisting of digital circuits, processors, memory, and I/O devices. Their main method of communication is via digital serial/parallel interfaces which is consist of clock and data interface. To ensure correct transmission of data from one system to another, that is the role of signal integrity check.
Problem
Digital signal is almost always transmitted with reference to a clock signal. The transmitter, transmission medium, and receiver are not perfect, and signal distortion can be easily introduced in form of voltage and timing error resulting in poor reception and detection of data. In this the text, we present commonly seen signal integrity problems, its cause, and address some best design practice to mitigate these problems.
Common Signal Integrity Problems
Impedance mismatch
impedance mismatch for high speed interface on a trace with transmission line effect causes signal reflection. We identify a trace of having a transmission line effect is by evaluate whether nor not the trace length exceeds at least 10 times the lowest electrical wavelength of the highest frequency signal.
Common cause
poor termination
if a signal at the receiving end is not terminated with same impedance as that of the transmission line, then signal reflection occurs.
Note: most of standard high speed interfaces such as USB have on-chip termination.
poor controlled impedance
every high speed signal will either have ~50 ohms impedance for single ended trace or 100 ohms for differential signals, hence the transmission medium (copper trace on PCB) needs to have certain width and height to achieve the right trace impedance (i.e characteristic impedance of the trace)
Length mismatch(timing skews) for differential signaling
Intrapair
intrapair skew is the length difference between P and N trace within a pair. Large intrapair skew cause receiver to poorly detect logic 0 or 1 voltage levels.
interpair
interpair skew is the length different between two pairs of signals with a communication bus. it's often the difference between data and clock. excessive interpair skew causes receiver not to detect the right logic levels at the right clock edges. Remember most of the digital communication serial interface is source synchronous (i.e data is clocked in by the receiver on either rising edge or falling edge of the clock from the transmitter).
length mismatch causes timing errors
Cross-talk
Cross-talk happens when a near by signal trace has an induced noise voltage due to signal coupling from a nearby high speed signals. This induced noise voltage causes signal integrity to go down resulting in proper detection of logic 1 or 0s from the receiver.
Path loss
energy of high frequency component of a signal is absorbed by the dielectric material of the transmission medium (in case of PCB, it's the fiberglass material FR4) hence resulting in signal attenuation.
another cause of path loss is the conduction loss of the trace, at higher speed, the resistance of the copper trace increases due to skin effect. This increase in resistance further attenuates signal strength.
Test setup
Always measure at receiver end
small test points with minimal stub located at the receiver end of trace for probing.
Use correct bandwidth oscilloscope and probe bandwidth and isolation forthe desired signal frequency
Passive vs Active probe
Use passive probe for lower speed interface and sanity check such as frequency of a clock
use active probe for higher speed interface for signal integrity validation such as rise/pass time. Probe tip capacitance will add additional capacitive load on the high speed interface cause higher rise and fall time.
Diagnostic
Eye diagram
A eye diagram is a quick and instant visual check on timing and voltage margin of the signal received the receiver. The more open the eye has the higher the margin for receiver to detect logic 1 or 0s. Various high speed interface has its own eye opening requirements. Generally a eye mask, indicator of timing and voltage margin, for various serial interface is standardized in the industry that that it can be use to determined the signal integrity of the interface.
All errors found on Eye Diagram are lumped into two categories, timing and voltage.
Timing Errors (Horizontal (i.e timing/phase noise))
Setup and Holdtime
The setup and holdtime is minimum of time with respect to clock that the data needs to be held stable at the receiver side in order for receiver to correctly detect and capture the input data.
Rise and fall time
signal rise and fall time impacts eye opening of a signal causing signal detection performance of the receiver. For instance, slow rise and fall time closes the eye opening of the eye diagram.
Skew/phase noise
Timing offset between received signal and it's reference clock needs is the skew noise. This skew closes the width of the eye diminishing the margin of safety for signal tranmission.
Jitter
Two types
Deterministic jitter
Bounded and predictable
Caused by:
Reflection due to impedance discontinuity
Crosstalk (bounded uncorrelated)
Internal I/O pad power supply noise modulated to the driver circuit
External power supply noise coupled to the data line
Nearby high speed coupling via mutual capacitance or inductance
Data Dependent
Duty cycle distortion
Inter symbol interference
Random jitter
Unbounded and unpredictable
Follows a normal distribution
Caused by:
Clock Generator design
Crystal Tolerance
Frequency deviation (PPM)
Manufacturing tolerance (PPM)
Aging (PPM)
PLL Design
thermal noise - proportional to temperature
shot noise - proportional to bias current/power
pink noise - proportional to 1/f
Metrics
Total Jitter is measured as given bit error ratio (BER) expressed by combination of RJ (expressed as RMS standard deviation) and DJ ( expressed as Peak2Peak)
Equation
Total Jitter = n*RJ+DJ
Voltage Errors (Vertical (i.e voltage ripple))
Voltage levels deviation from ideal logic 1 or 0 level is generally the cause of signal reflection due to impedance mistanch and signal attenuation due to path loss.
This voltage error closes the eye opening in the vertical direction.
Mitigation
Layout
Impedance Matching reduces reflection. Following best practice should be evaluated and followed.
Near end termination
Far end termination
Star connection
Daisy chain connection
cross-talk reduction
have at least 2 to 3x width spacing between line to line and line to pad.
reduce running two different interface in parallel
Separate sensitive signals on separate layers with routing in perpendicular to each other
this reduce capactive coupling between interfaces.
Route signals if possible between two good reference ground layers.
Timing Skew
Intra-pair (within a differential pair [i.e P to N matching)
Static phase control
match the over all signal trace length.
Dynamic phase control
match the length along every point of the signal trace
additional benefit is EMI Reduction
Inter pair (between a differential pair [i.e Data to Clock matching)
Transmitter configuration
Pre-emphasis
high frequency signal spectrum boosts to reduce signal attenuation due to path loss
select higher drive strength to increase voltage margin.
Redriver
redriver circuit helps boost signal strength when transmitting along a loss trace or cable
Note: rederiver circuit can cause EMI issue due to high drive strength. It needs to be shielded inside a shield can.
Summary and Conclusion
learned about common signal integrity problems
understand importance of test equipment and setup
overview voltage and timing errors of eye diagram
learn about best practice of signal integrity mitigation from a board level design.
Almost all electronics design has been digitized in modern time. As a system engineer focusing on digital system, ensuring signal integrity in digital communication system is critical to the over functionality of your computing system or else control and data can't not be communicated reliable across all digital subsystems.
Reference and Further Reading
"The Three Most Confusing Topics in Signal Integrity ", http://web.mst.edu/~jfan/slides/bogatin1.pdf