Lane Bandwidth Calculation
The calculate the bandwidth required for each high speed data lane is needed to select the right interface that can handle the data throughput from the product performance such as video streaming or camera capture.
Bandwidth is measured in Hz
Link is consisting for multiple data lanes
In MIPI DSI DPhy = a link has 4 data lanes
Find the per lane bandwidth requirements for MIPI DSI 4 Lane interface for a FHD display (1920*1080) at 60 frames per second.
Total Pixel size [bit] = 1920*1080*3*8 = 49766400 bits (there are three colors (RGB) per pixel and each color is has 8bit resolution)
Total raw video throughput [bit / sec] without compression = Total Pixel Size*Frame Rate = 49766400 bits*60 Hz/Sec = 2985984000 bits/sec
Total DSI link throughput [bit / sec] 1:3 video compression =Total raw video throughput * compression ratio = 2985984000 bits/sec * 1/3 = 995328000 bits/sec
Total DSI per lane throughputc [bit /sec] = 995328000/4= 248832000 [bits/sec]
Bandwidth (i.e data clock frequency)[Hz] =248832000/2( i.e 2 bits per one clock frequency such as DDR) = 124416000 Hz = 124 MHz