Memory

Created: May 2020Last Updated: 10/13/2020

Introduction

Have you wonder how your smart electronics load, process, and store picture quickly? Or how the applications can be opened in instantly on your smart phones? A main memory is critical is a embedded system design that meets the fast read and write requirements for low latency user experience.

background

Volatile memory: It means that the memory needs to be constantly powered on to retain its data.

Non volatile memory: it means the memory can retains its data when powered off.

Random Access Memory (RAM): It's the main memory that a modern embedded system CPU uses to execute programs and stores data.

Read only memory (ROM): It's a nonvolatile memory that is pre-programmed at manufacturing stage, so end users cannot reprogram it. It stores the very first program that the computer needs to boot.

Two types of RAM

  • DRAM

    • Made up of single transistor and a capacitor

    • higher memory per die size density

    • lower cost

      • Types of DRAM

        • Synchronous DRAM (SDRAM)

          • DRAM is read/write is synced by processor clock speed.

        • Double Data Rate (DDR SDRAM)

          • Double data rate is a data transfer technology that clocks the data on both rising and falling edges of the memory clock.

            • Typical DDR memory versions are DDR3, DDR4, LPDDR4, etc.

  • SRAM

    • made up of 6 transistors, so low memory per die size density

    • Faster than DRAM

    • higher cost

DDR DRAM Fundamentals

Architecture

    • DDR DRAM is made of a DRAM controller and a memory cell

    • Memory cell is a collection of memory arrays (N Rows X M Columns, Type. M =8bits) organized into banks on a single IC package.

      • Each bank contains typ. ~1k columns ( 10 bit column addresses), hence a total of 8K bits per row.

      • Each bank contains typ. ~8k rows (13 bit row addressed), henec a total of 8k rows.

        • Total memory per bank is = 8k*8kbits=64 Mbits

      • Typical DDR3 Memory contains 8 banks (i.e 3 bit bank address)

        • Total memory is 64 Mbits * 8 = 512 Mb

      • DRAM controller access a memory cell using bank address, address and command signals, row access strobe (RAS) and column access strobe (CAS).

        • Address Bus = ADDR

        • Bank address = BA

        • Bank group address = BA

        • Row Access Strobe (RAS)

          • asserting this signal on DRAM means the address on ADDR line is the row address

        • Column access strobe (CAS)

          • asserting this signal on DRAM means the address on ADDR line is the column address

        • DQ (Data input/output) Bus

          • typical 4,8,16 bits wide

        • DQS ( Data Strobe)

          • It's an output for read and input for write data needed for correct data timing.

Memory Accessing flow

  • Select a bank group

  • Select a bank

  • Activate a row (DRAM reads from ADDR pin when RAS pin is asserted)

  • Activate a column (DRAM reads from ADDR pin when CAS pin is asserted)

  • Data output to DQ (Data input/output bus)

Performance Parameters

      • Column Access Strobe latency (CL)

        • It's the time delay between read command to when the data is available specified in terms of clock cycles.

        • this parameter is generally used to evaluate the memory accessing time performance.

      • DDR bandwidth

        • DDR3 SDRAM

        • 1866 Mb/s, 2133 Mb/s, 2400 Mb/s

        • DDR4 SDRAM

        • 2400 Mb/s, 3200 Mb/s

      • Voltage Level

        • DDR3/DDR3L 3.3V/1.5V typ.

          • Note: postfix -L standards for low voltage variant.

        • DDR4 1.2V typ.

Practical Design Analysis

Design goal: 2 giga byte (GB) DDR4 Memory

Background:

    • DDR size is comes with density in giga bits (Gb) organized in different I/O bus width (typ 4, 8 or 16)

    • SoC supports supports 32 bit width memory interface up to 4 GB total memory addresses.

DDR selection:

    • Choose DDR4 part with density of 8 Gb (1GB) and I/O bus width of 16 bits (x16)

    • Compare CAS Latency among various vendors and choose the lowest .

    • Connect two of them in cascade to fulfill 32 bit SoC memory bus width.

DDR Vendors:

  • Samsung

  • Sk Hynix

  • Micron

Q&A

    • What determines memory performance?

      • CAS Latency is the bottle neck of memory throughput.

    • What is the actual data rate/bandwidth of the memory?

      • Transfer rate is 2x of I/O bus clock for DDR (double data rate). Hence if the selected memory I/O bus width is 16 bits, then total data rate is MT/s * I/O bus width.

        • Example: a 200 MHz memory clock rate DDR4 memory will have a transfer rate for 400 MT/s with 8 bit with bus will have Bandwidth (total data rate) of 3200 Mb/s)

    • What prevents all devices using DDR4 memories?

      • DDR4 has a benefit of lower power consumption at higher data rate but is generally quite expensive compared to DDR3. Cost of memory will go down eventually when market has reached above a certain DDR4 volume that allows DDR3 to DDR4 transition.

Summary & Conclusion

  • DDR doubles the transfer rate per clock cycle

  • Synchronous memory sync the DRAM with processor operating clock/

  • Main memory of modern smart device is powered by DDR3/DDR4 SDRAMs.

  • CAS Latency is the bottle neck of memory throughput

  • Part cost is what keeps electronic from using the better DDR technology.

DRAM is the main system memory that keeps the main processor running at low memory accessing latency. Choosing the correct memory, bandwidth, density, I/O bus width, and latency is essential for over all performance of the product. As an electronic system engineer, working with software team on obtaining memory performance metrics and requirements is needed before choosing a appropriate DRAM form the product.