Low Speed Digital Interface Basics


Inter IC communication has been established and evolved since early days of electronic design. Few of these basic interface stands the test of time and have been wide adopted across electronic industry. We will examine few basic and popular interfaces such as, I2C, SPI, and UART that are used in almost any embedded system today.


Digital communication largely fulfills two goals, send instructions (i.e control commands) and transfer data:

  • Control commands initializes and configures device for operation.
  • Transfer data between on board memory and peripheral devices are needed for data keep embedded system running as intended.

I/O Output Type

Open Drain

  • An I/O output design where external resistor is used to pull the interface to logic high and the internal NMOS transistor is used to drive the interface low.

Push pull

  • An I/O output design where a complementary pair of PMOS and NMOS transistor is used to drive the interface to logic level high or low.

Data transfer Structure


  • Data is sent and receive one bit at time in a sequential manner
  • Minimal communication interface and logic are needed at expense of lower data rate.


  • Data is sent and received in multiple bits at a time in a parallel manner.
  • Higher data rate can be achieved but at expense complex communication interface and logic

Data Transfer Technique


  • Data is transmit and received with a clock signal in fix time interval

Source Synchronous Clocking

  • Transmitter device generates the clock needed for synchronous communication.
  • This clocking technique is widely used in practice.


  • Data is transmit and received without a a clock in a random time interval



Main Purpose

  • Commonly used for issuing instructions and establish handshakes.
  • For slow output data device such as a sensor, it is also used to transfer data.

Main features

  • Supports multiple master and slave devices on one I2C bus
  • Half Duplex
  • Slow data rate (Typ. 400 kHz)
  • Open drain output
    • note: Open drain output allows two things: flexible bus voltage and multiple device using the same bus.

BUS Pins

  • SDA - Data
  • SCL -Clock

Protocol Basics

  • Start Bit -> Slave address -> Command/Data ->Stop Bit
  • 7bits slave addressing
    • 7 bits addressing allows 2^7 =128 unique slave addresses; however in practice it's impractical to have all I2C devices on one bus due to limited bus bandwidth (i.e high I2C link overheads and low clock speeds for transactions)
  • 8 bits packet frame
  • Arbitration
    • Master releases data line to high and immediately check whether or not line is still low. if line is still low, then other master device is still using it.
    • This avoids bus contention and allows multiple drivers to be on the same data line.
  • Slave Clock Stretching
    • If slave needs more time to process the current data before next data frame is transferred, then slave holds the clock line low to let master know that it needs more time, hence, slave stretches the clock.

Helpful Software Debug Tool

  • A set of I2C Linux shell commands using Linux i2c-tools package.
    • Note: One has to download and install the tool on Linux machine.

Debug Hardware Tool

  • A I2C logic analyzer can be used to sniff, read, and write on I2C bus
    • Salae logic analyzer & Aardvark I2C/SPI Host Adapter
    • Note: These two logic analyzers comes with its own analysis software


Main Purpose

  • It is used generally used for transfer data due to higher speed.

Main Features

  • Full duplex
  • High date rate (Typ. 20 MHz)
  • Push and Pull output
    • Note: Push and Pull uses CMOS for output. With this driver type, only one driver can be allowed per data line to avoid bus contention unlike I2C where multiple drivers can be used per data line.

BUS Pins

  • MOSI - Master out slave in
    • Master device data output
  • MISO - Master in slave out
    • Master device data input
  • CLK - Clock
  • CS - Chip Select
    • Master device assert this pin to logic level high on slave device to start communication.

Debug Hardware Tool

  • A I2C logic analyser can be used to sniff, read, and write on I2C bus
    • Salae logic analyzer & Aardvark I2C/SPI Host Adapter
    • Note: These two logic analyzers comes with its own analysis software

UART (universal asynchronous receiver/transmitter)

Main Purpose

  • It is used generally used for sending control commands and load small firmware of devices used in debug.

Main features

Asynchronous Transmit and Receive

  • Host and Slave must agree on data rate (Baud Rate), packet length, stop, parity bit.

Slow data rate (typ. 9600 Baud Rate)

  • No Clock Interface


  • TX
  • RX

Helpful Serial Terminal Application

  • Coolterm

Debug External hardware Interface


What affects length of interconnects?

  • Line capacitance and signal reflection.
  • For I2C and UART, trace can be long (multiple 10s of cm range) due to lower clock speed in kHz range.
  • For SPI, trace needs to be shorter ( in the cm range) due to higher frequency clock speed in 10s of MHz.

How do I adjust drive strength to improve signal integrity?

  • For I2C, using a stronger pull resistor (i.e small resistor value in kohms range) improves rising and falling time.
  • For UART and SPI, an additional re-driver chip can be used.

Summary and Conclusion

  • Source Synchronous clocking is widely seen in inter-circuit digital communication, in which transmitter sends a clock signal along with data.
  • Asynchronous communication involves not using a clock as the data sync signal but rather on a predefined data rate, format, and starting and stop mechanism between two devices.
  • I2C and UART interface are used for control commands and slow data transfer
  • SPI is used for higher data transfer.

Slow digital interface are essential for all subsystem to initialize, handshake, and provide essential data for the entire system to work with each other.