Clock Generation and Distribution

Created: 7/12/2021Last Updated: 7/06/2023


Clocks are needed for various functions of a computing device containing processor, memory, and input and output peripherals. Each of these components requires different clock speeds specified by different standards. The core operating frequency is in the gigaherts range, memory clocks speed is in hundreds of megahertz range, and I/O transceivers interface can be slow as 10s of KHz to fast in the giga herts range. 

All these clock speeds comes from a signal source of clocks that can be scale up or down to meet the needs of each components in a computing device. a clock generator takes a high quality clock source such as a crystal oscillator and scales up using a phase locked loop and then divided down to various clock speeds needed in the system. Then various clock source are distributed to the target hardware blocks such as core, transceivers, and peripherals devices.

Pracical Design

Designing a clock tree for an FPGA (Field-Programmable Gate Array) involves several steps to ensure proper clock distribution and minimize skew. Here's a general outline of the process:


An example of Clock Generator IC


In reality, clock trees are more complex and involve multiple levels of buffering and distribution to account for factors like clock skew, fanout, and clock gating. Additionally, the clock tree may have a hierarchical structure with primary and secondary clock domains.

To design an efficient clock tree, various techniques are employed, such as buffer insertion, clock balancing, and clock meshing, to minimize clock skew and delay.

Further Reading:

An example of a Clock Tree: Page 3