Power Budget

Created 7/21/2021Last updated 7/21/2021

Introduction: Power budget is a limit to the total amount of power that can be deliver and used by the electronic product. This constraint comes from the power source such as a 500W power supply on your PC that can't not handle high performance graphic cards because the power load on the graphic cards exceeds the deliver capability of the power supply.

Practical Design Steps

  1. Document the power consumption of each subsystem (memory, graphic card, processor) in terms voltage, current, and power output.

  2. Evaluate the power efficiency of the regulators that supplies these subsystems.

  3. Find out the input power to these regulators by diving the output power by the efficiency of the regulator

    1. SMPS efficiency can be find in the datasheet and is ~ 85% to 90% under high load

    2. LDO (low drop out linear regulator) efficiency is Vout/Vin

  4. If subsystem shares the same input power rails, sum the total power output at this voltage stage.

  5. Do the same thing (summing power output) for the previous power stage.

  6. Work backwards all the way to the single power supply rail, and add up the total output power and current.

  7. Calculate how much power margin is left to the budget. (Reserve 20% headroom)

  8. If power margin is low, optimized the power stages to be more efficient

    1. reduce number of cascading stages

    2. use high efficient SMSP regulators

    3. sub-regulate linear regulators input voltage with a SMPS that is 300mV about the output voltage (i.e 1.5V vin for an LDO that regulates at 1.2V)

      1. Note: some regulator cannot have low drop out such as 300mV headroom and require large input voltage for biasing internal circuity (e.g. 1.7V vin min for an LDO that regulators at 1V). If the current is in the hundreds of miliampere range, this is acceptable. If the current is in the 1 to 2 ampere range, depending on the noise requirements, please use an SMPS or use a low drop out LDO that has lower input voltage limit

This exercise allows the designer to understand he power consumption at each power stage and optimize for power loss and therefore increase power margin of the system.

A fault happens such as power on reset when a surging power load transient exceeds the capability of the main power supply for a period of time and shuts down the system.