Design for Signal Integrity

Introduction

Signal integrity is crucial for maintaining the integrity of signal waveforms during transmission along physical mediums, such as copper traces on a printed circuit board (PCB). In modern board-level and system hardware designs, high-speed interconnects and networking pose significant challenges to signal integrity due to transmission effects caused by high-speed signaling.

Different Types of Signal Integrity Problems

• Reflection: Voltage ripple noise resulting from impedance discontinuity causes distorted waveforms at both the transmitter and receiver ends.

• Crosstalk: Voltage ripple noise caused by mutual coupling between two or more adjacent traces leads to distorted waveforms at both the transmitter and receiver ends.

• Signal Attenuation: Voltage swing observed at the receiver end is reduced due to dielectric losses and PCB trace resistance (considering phenomena like skin effect) along the transmission line path, particularly in the case of long copper traces.

Common Problems

• Impedance Discontinuity: For instance, when a high-speed driver is connected via a Flexible Printed Circuit Board (FPCB) to a daughter card using a common-mode choke and ESD diodes, impedance discontinuity may occur. To mitigate this, it is crucial to control the impedance of high-speed traces, such as targeting a value of 90 ohms +/- 10%.

• Signal Attenuation: Excessive insertion loss can reduce voltage swing, leading to eye diagrams closing. To address this, it is essential to limit the total trace length to meet the physical layer requirements for each high-speed interface, as outlined in routing guidelines provided by chip vendors. Techniques like preemphasis can be employed to boost the high-frequency content of the signal. Performing signal integrity simulations can help verify the quality of eye opening in physical layer waveforms.

Mitigation

Reduce stubs and uncessary test points.

ESD pads introduce additional capacitance, which can cause impedance discontinuity. To minimize impedance changes, it is recommended to reduce the mounting capacitance of ESD diodes by incorporating a ground void directly underneath the signal pad. Additionally, selecting ESD diodes with low intrinsic capacitance is advisable. 

For connector pins, one can consider voiding the signal ground or using differential signaling, which exhibits lower dependence on ground layers.

High-Speed Interfaces

Type C USB (data transfer), Display Port (DP) (display), embedded Display Port (eDP) (display), MIPI CSI (Camera), PCIE (WiFi), DDR3/DDR4/LPDDR4/4x (DRAM), UFS3.0/eMMC5.1 (Flash Memory), etc.

Summary

Signal integrity is critical for ensuring the proper transmission of signal waveforms along physical mediums like copper traces on a PCB. High-speed interconnects and networking pose challenges to signal integrity due to reflection, crosstalk, and signal attenuation. Impedance discontinuity, one common problem, can be mitigated by controlling the impedance of high-speed traces. Signal attenuation can be addressed by adhering to trace length limits and employing techniques like preemphasis. Performing signal integrity simulations helps verify waveform quality.

For high-speed interfaces such as Type C USB, Display Port, MIPI CSI, PCIE, DDR3/DDR4/LPDDR4/4x, UFS3.0/eMMC5.1, maintaining signal integrity is crucial. Mitigation strategies include minimizing impedance changes caused by ESD pads, selecting diodes with low intrinsic capacitance, and utilizing techniques like ground voiding and differential signaling.

By understanding and effectively mitigating signal integrity problems, designers can ensure reliable and high-quality signal transmission in modern high-speed electronic systems.