Design for Signal Integrity

Introduction: signal integrity ensures proper signal waveform to be transferred along the physical medium such as copper trace on a printed circuit board. For today's board level/system hardware design, high speed interconnect/networking is a signal integrity challenge due to transmission effect as a result of high speed signaling.

Four Types of Signal Integrity problems

Reflection: voltage ripple noise cause by reflection due to impedance discontinuity causes distorted waveform seen at both transmitter and receiver ends

Crosstalk : voltage ripple nose caused by mutual coupling between 2 more or adjacent traces causes distorted waveform seen at both transmitter and receiver ends

Signal Attenuation: voltage swing see at the receiver end is lowered due to both dielectric loss and pcb trace resistance (see skin effect) along the tranmission line path (i.e long copper trace)

Common Problems and Mitigation

Impedance discontinuity

Example: A high speed driver is connect via a FPCB board to a daughter card through common mode choke and ESD diodes.

from the above

Control impedance for high speed traces.

90 ohms +/- 10% for

Signal attenuation: insertion loss becomes large and can cause the voltage swing to reduce and cause eye diagram to close.

  • Must limit the total trace length to be under the physical layer requirement for each high speed interface per routingguideline given by the chip vendor.

  • Preemphsis can be used to boost high frequency content of the signal

  • Perform signal integrity simulation to verify the eye opening physical layer waveforms.

High Speed interface: Type C USB (data transfer), Display Port (DP) (Display), embedded Display Port (eDP) (display), MIPI CSI (Camera), PCIE (WiFi), DDR3/DDR4/LPDDR4/4x(DRAM), UFS3.0/eMMC5.1 (Flash Memory), etc.

Signal Integrity Mitigation

  • ESD pads have additional capacitance that introduced impedance discontinuity. In order to minize impedance changes, one can to reduce mounting capacitance of the ESD diode by having a ground void directly underneath the signal pad.

  • Choose an ESD diode that has low intrinsic capacitance

  • for connector pins, one can also void the signal ground or use differential signaling which has lower

  • dependence on ground layers.