High Speed Digital Interface Basics

Introduction

In an increasingly high data and widely connected world, high bandwidth and low latency is needed for an embedded system to transfer and process on demand service such as streaming, gaming, etc. High speed interconnects are essential for electronic system engineers to ensure proper data transfer

Background

Differential signaling: a common signal transmission method to increase noise immunity and increase signal bandwidth (i.e data rate)

Double Data Rate: it's a data rate enhancement technique to samples data at both rising edge and falling edge of the clock hence doubling the data rate.

Clock and Data Recovery (CDR): it's a hardware block that extracts clock from incoming asynchronous data for proper data sampling.

SerDes (Serializer/Deseralizer): it's a hardware block that converts between serial data to parallel interface due to limited pins on the digital ICs.

Commonly used Interfaces

USB

Main Features

Asynchronous, Clock Data Recovery, Differential signaling
High data rate (e.g. USB2.0 High Speed 480 Mbps, USB3.0 Superspeed 5Gbps)
A single USB host port can support 127 connected USB devices

Application

External USB mass storage
Human Interface Devices (HID)
- e.g. USB Keyboard, mouse, and game controller are exampled of HID.
Audio Streaming transport
- e.g. USB audio headphone, speakers, microphone.

Main Connectors:

Type A, Micro B, and C.

PCIE

Differential Signaling
each lane is full Duplex (i.e contains a transmitter and receiver)
Synchronous
High data rate
- 985 MBps per lane PCIE V3.0 Gen 1
Point to Point communication

Application

Wi-FI module (1 lane)
Main Storage SSD (4 lanes)
Graphic card (16 lane)

DDR

Main Feature

double data rate (DDR4 3200 MT/S)
source synchronous
High bus width (typ. 8bit wide).
- Note: Common DDR memory parts are rated by column width (e.g. 4, 8, 16 bit wide.) So a common solution to achieve a total amount of RAM is column cascading (i.e using two x4 DDR parts to match 8 bit wide memory bus where higher bus bits (A4 to A7 ) is connected tot he first DDR part, and lower 4 bits (A0 to A3) of the bus is connected to the 2nd DDR part.

Application

Interface DRAM memory with host processor.

SDIO (Secure Digital Input and Output)

Main Feature

High data rate
- 832 Mbps SDIO V3.0
Simple interface
- Data, Clock, 7 Command.
- Small pin counts, 9 pins for an external SD card. 6 pins for an internal embedded chip.
- 1 bit Bus Mode or 4 bit Bus Mode
Source Synchronous

Application

SD Memory Card access
Wireless communication interface

Q&A

Summary and Conclusion

Double Data Rate is a bus operation mode that essentially doubles the data rate by clocking data at both rising and falling edge for each clock period.
Most of ultra high speed interface uses differential signaling to improve noise immunity
Asynchronous interface such as USB uses Clock Data Recovery circuit to extract data clock and uses it to sample the incoming data.
PCIE are the highest bandwidth bus that is generally used for high data rate applications such as graphic card. It can go up to 16 duplex data lanes.
SDIO is commonly used for SD card memories or for wireless chips due to simple interface.

We learned common high speed interface and its basic applications within an electronics system. As a electronic system engineer, understanding and choosing the right interface is essential to meet today's demand of high data and low latency operations.

High Speed Digital Interface Basics

Introduction

Background

Q&A

Summary and Conclusion

Further Reading