FLoor Planning

Created: 5/13/2020Last Updated: 5/29/2020

Introduction

Floorplanning is placement at the intersection of high speed and power domains. Of course, you start with the predetermined locations, connectors, mounting holes, keep-out areas etc. Parts on both sides of the board is a cost driver but often the only way to go.

The real estate around the microprocessor/mega-processor is the most expensive on the board. Anything that can be at a distance should be since so many other components (memory, bypass caps, crystals, etc.) want to live close in.

On the other hand, some things would rather be out in the hinterlands. All of the sensors and analog devices come to mind; proximity, compass, camera, GPS, etc.

Lower speed or seldom used interfaces such as the keyboard, touchpad, fingerprint and haptics sensors end up with their connectors in the middle ground. In general, most connectorized features like the display port, camera, PCIe, USB and so on will also be locked down by the physical design.

Most boards will have a mix of the three classes so then the voltage domains come into play where you still have some latitude. 5V, 3.3V, 2.8V <--often a noisy power zone, and 1.2V should be grouped to allow elegant power planes using one or two layers. It all branches out from the power tree's root voltage. The priorities follow the pattern established above.

Background

Mechanical Component Outline (MCO): this is the PCB board outline given by the mechanical product design team that all electrical and mechanical components need to be fit within.

Design Overview

  • PCB area must be sufficient to fit all components as defined by MCO
  • Power supply needs to be isolated from low noise components such as radio and sensors.
  • ESD and noise filter needs to be placed at the source.
    • ESD at connector
    • Power filter at output of voltage regulator
    • RF filter cap at the impedance discontinuity point (i.e connector pins)
  • Decoupling capacitors needs to be placed right at the digital IC voltage pins
  • Passives capacitors and inductors for voltage regulator needs to be placed as compact as possible to the regulator IC.
  • Antenna needs to be isolated from noise source such as processor, system memory, and power supply.
  • High design pin count device (i.e process) needs to oriented in way to align the trace routing breakout direction
    • e.g., High speed memory I/O needs to be oriented on side that is closet to the memory package.

Summary and Conclusion

  • Placement study ensures all components can fit inside the board outline.
  • Isolate noisy component.
  • Component orientation must be angled to best breakout high speed interface.

Further Reading

N/A